1. Technical Field
The embodiment described herein relates to a semiconductor memory apparatus and, more particularly, to a buffer circuit of the semiconductor memory apparatus.
2. Related Art
A general buffer circuit includes first to fifth transistors N1 to N3, P1, and P2 as shown in FIG. 1. The first transistor N1 is applied with a reference voltage ‘Vref’ at a gate thereof. The second transistor N2 receives an input signal ‘in’ at a gate thereof. The third transistor N3 is applied with a bias voltage ‘Bias’ at a gate thereof. A node that is connected to a source of the first transistor N1 and a source of the second transistor N2 is connected to a drain of the third transistor N3. A ground terminal VSS is connected to a source of the third transistor N3. The drain of the first transistor N1 is connected to a gate and a drain of the fourth transistor P1. The fourth transistor P1 is applied with an external voltage VDD at a source thereof. The gate of the fourth transistor P1 is connected to a gate of the fifth transistor P2 and the drain of the second transistor N2 is connected to a drain of the fifth transistor P2. The fifth transistor P2 is applied with the external voltage VDD at a source thereof. At this time, an output signal ‘outb’ is outputted from a node that is connected to the second transistor N2 and the fifth transistor P2.
The general buffer circuit having the above-mentioned structure has a disadvantage in that a noise of the reference voltage ‘Vref’ varies a swing level of the output signal ‘outb’. Detailed description will be made below. When a voltage level of the reference voltage ‘Vref’ increases, a turn-on degree of the first transistor N1 increases, such that turn-on degrees of the fourth and fifth transistors P1 and P2 increase. Accordingly, a swing voltage level of the output signal ‘outb’ increases. If the input signal ‘in’ is a clock signal, the clock signal is outputted as a clock signal having a duty ratio different from a duty ratio of the input signal ‘in’ due to the increase in the swing voltage level of the output signal ‘outb’. Further, when the voltage level of the reference voltage ‘Vref’ decreases, the swing voltage level of the output signal ‘outb’ decreases. Therefore, if the input signal ‘in’ is the clock signal, the clock signal is outputted as a clock signal having a duty ratio different from the duty ratio of the input signal ‘in’ due to the decrease of the swing voltage level of the output signal ‘outb’.